Semiconductor device and method of manufacturing the same

ABSTRACT

A method of manufacturing a semiconductor device includes the steps of forming barrier metals on first electrodes provided on a chip of the semiconductor device, implementing a predetermined test on the semiconductor device by applying a signal to the semiconductor device via at least one of the barrier metals, and forming second protruded electrodes on the barrier metals. The predetermined tests are implemented before forming second protruded electrodes on the barrier metals.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a semiconductor deviceand a method of manufacturing the same. The present inventionparticularly relates to a method of manufacturing a semiconductor deviceprovided with electrodes formed on a semiconductor substrate, barriermetals formed on respective electrodes and protruded electrodes joinedto the electrodes via the barrier metals.

[0003] Recently, there is a decrease in the sizes of semiconductordevices. It is known to use protruded electrodes such as bumps asexternal connection terminals of the miniaturized semiconductor devices.The semiconductor devices having protruded electrodes may be a BGA (BallGrid Array) type semiconductor device or a CSP (Chip Size Package) typesemiconductor device.

[0004] Also, the semiconductor devices require higher reliability, andthus, it is necessary that protruded electrodes also realize higherreliability.

[0005] 2. Description of the Related Art

[0006]FIG. 1 is a side view of an example of a semiconductor device of arelated art having bumps and electrode pads. Here, FIG. 1 shows asemiconductor device 1 of a general CSP type. As shown in FIG. 1, thesemiconductor device 1 has a plurality of electrode pads 3 provided on acircuit forming surface 2 a of the semiconductor chip 2. Each electrodepad 3 is provided with a bump 4 which serves as an external connectionterminal.

[0007]FIG. 2 is an enlarged view showing a region around the electrodepad 3 provided on the semiconductor device 1 of FIG. 1. The electrodepad 3 includes an electrode 5 and a barrier metal 10. As shown in FIG.2, the bump 4 is not directly formed on the electrode 5, but is joinedto the electrode 5 via the barrier metal 10 provided on the electrode 5.The detailed structure of the semiconductor device 1 will be describedbelow.

[0008] The circuit forming surface 2 a of the semiconductor chip 2 isprovided with an insulating layer 6 for protecting the circuit formingsurface 2 a. The insulating layer 6 is provided with openings 7 atpositions corresponding to the electrodes 5 such that the electrodes 5are exposed via the openings 7.

[0009] The barrier metal 10 has a layered structure of a firstconductive metal layer 11, a second conductive metal layer 12, and athird conductive metal layer 13. The barrier metal 10 prevents the bump4 from diffusing into the electrode 5. For example, when the bump 4 ismade of solder and a gold (Au) plating is applied on the electrode 5,and if the bump 4 is directly joined to the electrode 5, the solder willdiffuse into the gold plating of the electrode 5. This causes a decreasein strength of the diffused part, which may result in the peeling off ofthe bump 4 from the electrode 5. The barrier metal 10 prevents the bump4 from diffusing into the electrode 5 and thus prevents the bump 4 frombeing peeled off from the electrode 5.

[0010] The first conductive metal layer 11 is provided at a positionnearest to the semiconductor chip 2 or at the lowermost position. Thisfirst conductive metal layer 11 is made of a material having a goodjoining property with the electrode 5. The second conductive metal layer12 is provided on the first conductive metal layer 11. This secondconductive metal layer 12 is made of a material having a good joiningproperty with the first conductive metal layer 11. The third conductivemetal layer 13 is provided on the second conductive metal layer 12. Thisthird conductive metal layer 13 is made of a material having a goodjoining property with the second conductive metal layer 12 and the bump4. Also, the third conductive metal layer 13 should be made of amaterial which can prevent the diffusion of the bump 4.

[0011] The semiconductor device 1 is manufactured in the followingmanner. First, the barrier metals 10 are formed. In order to manufacturethe barrier metal 10, the first conductive metal layer 11 is formed onthe semiconductor chip 2 such that the first conductive metal layer 11is electrically connected to the electrode 5. Then, the secondconductive metal layer 12 is laminated on the first conductive metallayer 11. Subsequently, a resist having openings corresponding topredetermined shapes of the barrier metals is formed on the secondconductive metal layer 12. With this resist being provided on the secondconductive metal layer, the third conductive metal layer 13 is formed.Thereafter, the resist is removed. Further, unwanted parts of the firstand second conductive metal layers 11 and 12 are removed by etching.Thus, the barrier metal 10 is obtained.

[0012] The bumps 4 serving as external connection terminals are formedby transferring solder balls onto the barrier metals 10 and heating thesolder balls so that the solder balls will be joined to the barriermetals 10.

[0013] After the bumps 4 have been formed as described above, a testingstep is carried out. As shown in FIG. 3, probes 14 connected to a testeror a testing device (not shown) are brought in contact with the bumps 4.This may be referred to as “probing”. Then, test signals from the testerare supplied to the semiconductor chip 2 via the probes 4. Thus, apredetermined test such as a reliability test or an operational test canbe implemented on the semiconductor chip 2. Thereby, good semiconductordevices are selected.

[0014] With the method of manufacturing the semiconductor device of therelated art, the testing step is carried out after the bumps 4 have beenformed on the barrier metals 10. Therefore, the probes 14 should beconnected to the bump 4. However, it is difficult to properly connectthe probe 14 to the bump 4 having a spherical shape. Also, according tothe recent miniaturization of the semiconductor device 1, furtherfine-pitched structures, such as an area array, have been introduced.Then, there arises a problem that it is even more difficult to properlyconnect the probe 14 to the bump 4 having a spherical shape.

[0015] Also, when the probe 14 is directly probed on the bump 4, thematerial of the bump 4 will adhere to the tip part of the probe 14.Examples of the material forming the bump 4 may be tin (Sn) or lead(Pb). On the other hand, generally, the tip part of the probe 14 isprovided with a plated part 15. For example, when the probe 14 is madeof palladium (Pd), the plated part 15 may be of gold.

[0016] It is well known that tin reacts with gold. Therefore, if thematerial of the bump 4 adheres onto the tip part of the probe 14, theprobe 14 will be degraded over a several usage. This results in adrawback that the reliability of the testing step is reduced. Also,there is a drawback that the testing cost increases since a frequentreplacement of the costly probes 14 is necessary.

SUMMARY OF THE INVENTION

[0017] Accordingly, it is a general object of the present invention toprovide a method and a device of manufacturing a semiconductor devicewhich can overcome the drawbacks described above.

[0018] It is another and more specific object of the present inventionto provide method and a device of manufacturing a semiconductor devicewhich can improve the reliability of the testing step while reducing thecost of the testing step.

[0019] In order to achieve the above objects according to the presentinvention, a method of manufacturing a semiconductor device includes thesteps of:

[0020] a) forming barrier metals on first electrodes provided on a chipof the semiconductor device;

[0021] b) implementing, after the step a), a predetermined test on thesemiconductor device by applying a signal to the semiconductor devicevia at least one of the barrier metals; and

[0022] c) forming, after the step a), second protruded electrodes on thebarrier metals.

[0023] With the method described above, connection terminals (e.g.,probes) for testing used in the testing step are not connected to thespherical protruded electrodes but connected to the barrier metal havingsubstantially flat surfaces. Therefore, the connection terminals fortesting can be securely connected to the barrier metals.

[0024] It is still another object of the present invention to providemethod and a device of manufacturing a semiconductor device which canreduce the cost of the testing step while improving the reliability ofthe testing step. Thereby, reliability test such as an electric test anda burn-in test can be implemented with a high reliablity.

[0025] In order to achieve the above object, the step a) includes a stepof forming the barrier metals each having a multilayer structure havinguppermost conductive metal layer which is made of a material which canbe alloyed with a material of the second protruded electrodes and has aresistance to reaction and adhesion with a material of probes used forthe step b) and with a material of plated parts provided on the probes.

[0026] With the above structure, the reliability of the test can beimproved and there is no need for a frequent replacement of costlyprobes.

[0027] Other objects and further features of the present invention willbe apparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a side view of an example of a semiconductor device of arelated art having bumps and electrode pads.

[0029]FIG. 2 is an enlarged view showing a region around the electrodepad provided on the semiconductor device of FIG. 1.

[0030]FIG. 3 is diagram showing a testing step carried out in a methodof manufacturing a semiconductor device of the related art.

[0031] FIGS. 4 to 9 are diagrams showing various sub-steps of a barriermetal forming step of a first embodiment of a method of manufacturing asemiconductor device of the present invention.

[0032]FIG. 10 is a diagram showing an individualized semiconductor chipprovided with barrier metals.

[0033]FIGS. 11 and 12 are diagrams showing how the electrical test iscarried out on the semiconductor chip.

[0034]FIG. 13 is a diagram showing how the burn-in test is carried outon the semiconductor chip.

[0035]FIG. 14 is an enlarged view showing a region around the electrodepad provided on the semiconductor device of a first embodiment of thepresent invention.

[0036]FIG. 15 is a chart showing combinations of materials of the probeand the third conductive metal layer and possible materials of thefourth conductive metal layer.

[0037] FIGS. 16 to 19 are diagrams showing various barrier metal formingsteps of a second embodiment of a method of manufacturing asemiconductor device of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] In the following, principles and embodiments of the presentinvention will be described with reference to the accompanying drawings.

[0039] FIGS. 4 to 15 are diagrams illustrating a manufacturing method ofa semiconductor device 20 of a first embodiment of the presentinvention. In FIGS. 4 to 9, components similar to those shown in FIGS. 1to 3 are indicated with similar reference numerals.

[0040] First of all, for the sake of convenience, a structure of thesemiconductor device 20 to be manufactured will be described in detail.FIG. 14 is an enlarged view showing a region around an electrode pad 23provided on the semiconductor device 20 of a first embodiment of thepresent invention.

[0041] Referring to FIG. 14, the electrode pad 23 provided on thesemiconductor device 20 includes an electrode 5 formed on asemiconductor chip 27 and a barrier metal 30A formed on the electrode 5.The barrier metal 30A provided on the semiconductor device 20 of thepresent embodiment has a layered structure of a first conductive metallayer 31, a second conductive metal layer 32, a third conductive metallayer 33 and a fourth conductive metal layer 34.

[0042] The first conductive metal layer 31 is layered at a positionnearest to the semiconductor chip 2 so as to be joined to the electrode5. The first conductive metal layer 31 may also be referred to as alowermost conductive metal layer. This first conductive metal layer 31is made of a material having a good joining property with the electrode5. In the present embodiment, the first conductive metal layer 31 ismade of a material such as titanium (Ti) and has a thickness of about500 nm.

[0043] Instead of titanium, the first conductive metal layer 31 may bemade of a metal chosen from a group consisting of chromium (Cr),molybdenum (Mo) and tungsten (W), or of an alloy containing a metalchosen from a group consisting of titanium (Ti), chromium (Cr),molybdenum (Mo) and tungsten (W).

[0044] The second conductive metal layer 32 is interposed between thefirst conductive metal layer 31 and the third conductive metal layer 33.This second conductive metal layer 32 is made of a material having agood joining property with both the first conductive metal layer 31 andthe third conductive metal layer 33. In the present embodiment, thesecond conductive metal layer 32 is made of a material such as nickel(Ni) and has a thickness of about 500 nm.

[0045] Instead of nickel, the second conductive metal layer 32 may bemade of a metal chosen from a group consisting of copper (Cu) andpalladium (Pd), or of an alloy containing a metal chosen from a groupconsisting of copper (Cu), nickel (Ni) and palladium (Pd).

[0046] The third conductive metal layer 33 is interposed between thesecond conductive metal layer 32 and the fourth conductive metal layer34. This third conductive metal layer 33 is made of a material having agood joining property with both the second conductive metal layer 32 andthe fourth conductive metal layer 34. In the present embodiment, thethird conductive metal layer 33 is made of a material such as copper(Cu) and has a thickness of about 500 nm.

[0047] Instead of copper, the third conductive metal layer 33 may bemade of a metal chosen from a group consisting of nickel (Ni) andpalladium (Pd), or of an alloy containing a metal chosen from a groupconsisting of copper (Cu), nickel (Ni) and palladium (Pd).

[0048] The second conductive metal layer 32 and the third conductivemetal layer 33 are interposed between the first conductive metal layer31 (lowermost conductive layer) and the fourth conductive metal layer34. Thus, a combination of the second conductive metal layer 32 and thethird conductive metal layer 33 may also be referred to as anintermediate conductive layer.

[0049] The fourth conductive metal layer 34 is layered at a positiondistal from the semiconductor chip 2. The fourth conductive metal layer34 may also be referred to as an uppermost conductive metal layer. Thisfourth conductive metal layer 34 is made of a material which can beeasily alloyed with the material of a bump 35 and which has resistanceto oxidation. In the present embodiment, the material of the bump 35 issolder. Also, the fourth conductive metal layer 34 is made of a materialsuch as gold (Au) and has a thickness of about 0.1 μm.

[0050] Instead of gold, the fourth conductive metal layer 34 may be madeof a metal chosen from a group consisting of platinum (Pt), palladium(Pd), silver (Ag) and rhodium (Rh) or of an alloy containing a metalchosen from a group consisting of gold (Au), platinum (Pt), palladium(Pd), silver (Ag) and rhodium (Rh).

[0051] In the above described structure, each one of the first to fourthconductive metal layers 31 to 34 are described as a single metal layer.However, each one of the first to fourth conductive metal layers 31 to34 may also have a layered structure of a plurality of conductive metallayers.

[0052] The bump 35 is an example of a protruded electrode. It is to benote that the protruded electrode is not limited to a spherical ball butcan also take other shapes such as a stud bump. In the presentembodiment, the bump 35 serves as an external terminal and has asubstantially spherical shape. Considering a secure mounting of thesemiconductor device 20, the bump 35 is made of a material chosen so asto improve joining property with the mounting substrate. Thus, in thepresent embodiment, the bump 35 is made of solder which is an alloy oftin (Sn) and lead (Pb). For example, a solder having a Pb/Sn ratio of95%/5% is used. The bump 35 may have a height of about 100 μm.

[0053] Instead of solder, the bump 35 may be made of a metal chosen froma group consisting of tin (Sn), lead (Pb), silver (Ag), indium (In) andbismuth (Bi) or of an alloy containing a metal chosen from a groupconsisting of tin (Sn), lead (Pb), silver (Ag), indium (In) and bismuth(Bi). Any of the metals and alloys may be selected, as long as theselected metal or alloy has a low melting point of less than or equal toabout 350° C.

[0054] In the present embodiment, the fourth conductive metal layer 34is made of gold (Au) which can be easily alloyed with solder used as amaterial of the bump 35. Thus, a metal having a good joining propertywith the bump 35 may be selected as a material of the fourth conductivemetal layer 34, so as to improve the joining property between the fourthconductive metal layer 34 and the bump 35.

[0055] Also, the fourth conductive metal layer 34 is made of a materialhaving a good resistance to oxidation. Therefore, even if a heattreatment is implemented after the barrier metal 30A has been formed andthen the bump 35 is formed on the barrier metal 30A, an oxide layer willnot be formed on the surface of the fourth conductive metal layer 34during the heat treatment. This is advantageous since the oxide layerhas a negative effect for joining the bumps. Therefore, the bump 35 canbe securely joined on the barrier metal 30A, and thus the reliability ofthe semiconductor device 20 can be improved.

[0056] In the following, a method of manufacturing the semiconductordevice 20 of the above-described structure will be described.

[0057] Although the semiconductor device 20 is manufactured through anumber of steps, only those steps essential to the present inventionwill be described in detail. The following explanation relates to a stepof forming barrier metals (barrier metal forming step) a step of formingbumps (protruded electrode forming step), and a step of testing aplurality of semiconductor chips provided on a wafer (testing step).

[0058] FIGS. 4 to 9 are diagrams showing various sub-steps of thebarrier metal forming step of a first embodiment of a method ofmanufacturing a semiconductor device of the present invention. FIG. 4shows a part of a wafer 25 provided with the electrodes 5 and theinsulating layer 6 having the openings 7 through which the electrodes 5are exposed. It is to be noted that, as a result of other manufacturingsteps, the wafer 25 has already been provided with a plurality ofsemiconductor chips (not shown) integrated thereon. FIG. 4 is anenlarged view showing a region at one of the electrodes 5 provided onone of the plurality of semiconductor chips formed on the wafer 25.

[0059] As shown in FIG. 5, first of all, a first conductive metalcoating 41 is formed on the wafer 25 through a sputtering process. Then,a second conductive metal coating 42 is provided on the first conductivemetal coating 41. In the present embodiment, the first conductive metalcoating 41 may be made of titanium (Ti) and has a thickness of about 500nm. The second conductive metal coating 42 may be made of copper (Cu)and also has a thickness of about 500 nm.

[0060] As shown in FIG. 6, after the first and second conductive metalcoatings 41 and 42 have been formed, a positive resist 44 is provided onthe second conductive metal coating 42. Then, the positive resist 44undergoes an etching process so as to provide openings 45 formed atpositions corresponding to the electrodes 5. The opening 45 is formedwith an area greater than the area of the electrode 5.

[0061] Then, an electric current is applied to the first conductivemetal coating 41 or the second conductive metal coating 42. Then, anelectrolytic plating process is carried out so as to provide the thirdconductive metal layer 33 on the second conductive metal coating 42 andto provide the fourth conductive metal layer 34 on third conductivemetal layer 33. The third conductive metal layer 33 has a thickness ofabout 2 μm and the fourth conductive metal layer 34 has a thickness ofabout 0.1 μm. FIG. 7 is a diagram showing a state where the thirdconductive metal layer 33 and the fourth conductive metal layer 34 havebeen formed.

[0062] In the present embodiment, the third conductive metal layer 33 ismade of nickel (Ni) and the fourth conductive metal layer 34 is made ofgold (Au). Also, as has been described above, the fourth conductivemetal layer 34 is a thin metal layer having a thickness of about 0.1 μm.The weight of the fourth conductive metal layer 34 is less than 2%(weight percentage) of the weight of the bump 35 to be formed in theprotruded electrode forming process. The weight of the fourth conductivemetal layer 34 can be easily controlled by changing the currentconducting time and the plating current during the electrolytic platingprocess.

[0063] Also, as has been described above, the opening 7 provided in theresist 44 has an area greater than that of the electrode 5 (e.g., theopening has a size of φ110 μm). Therefore, since the resist 44 is usedas a mask, the fourth conductive metal layer 34 has an area greater thanthe area of the electrode 5. In detail, when viewed as a plan view, adiameter of the fourth conductive metal layer 34 is substantially thesame as a diameter of the bump 35. Also, since the first to fourthconductive metal layers 31 to 34 are laminated as a layered structure,the surface of the uppermost fourth conductive metal layer 34 will besubstantially flat.

[0064] After the third and fourth conductive metal layers 33, 34 areformed in the opening 45, the resist 44 is removed. Then, unwantedportions of the first and second conductive metal coatings 41, 42 areremoved by wet etching, so as to provide the first and second conductivelayers 31, 32, respectively. Thus, the barrier metal 30A having astructure shown in FIG. 9 is formed.

[0065] In the present embodiment, after the barrier metal forming step,the wafer 25 is diced so as to be separated into individualsemiconductor chips 27. FIG. 10 is a diagram showing the individualizedsemiconductor chip 27.

[0066] After individualizing the wafer 25 into the semiconductor chips27, the testing step is carried out on each semiconductor chip 27. FIGS.11 to 13 are diagrams showing the testing step.

[0067] In the present embodiment, the testing step includes anelectrical test and a burn-in test. FIGS. 11 and 12 are diagrams showinghow the electrical test is carried out on the semiconductor chip 27.First, a plurality of probes 14 connected to a tester is electricallyconnected to the semiconductor chip 27. The testing signals are suppliedto the semiconductor chip 27 via the probes 14. Then, based on theoutput signals from the semiconductor chip 27, it is determined whetherthe semiconductor chip 27 is good or bad.

[0068] As shown in FIGS. 11 and 12, in the present embodiment, theprobes 14 are connected to an upper part of the barrier metal 30A.

[0069] That is to say, in the present embodiment, the test step isimplemented after the barrier metal forming step and before theprotruded electrode forming step. Thus, at the time of implementing thetesting step, the bump 35 is not yet provided on the barrier metal 30A.Therefore, the semiconductor chip 27 can be tested by directlyconnecting the probe 14 to the barrier metal 30A.

[0070] As has been described, the fourth conductive metal layer 34positioned at the uppermost part of the barrier metal has acomparatively great area and is substantially flat. Therefore, the probe14 can be more securely connected to the barrier metal 30A (the fourthconductive metal layer 34) as compared to the method of the related artin which the probe 14 is connected to the spherical bump 4 (see FIG. 3).Thus, the test can be implemented with an improved reliability.

[0071] Also, the fourth conductive metal layer 34 is made of a materialhaving a good resistance to reaction and adhesion with the metal usedfor the probe 14. When the probe 14 is provided with the plated part 15,the fourth conductive metal layer 34 is made of a material having a goodresistance to reaction and adhesion with the metal used for the platedpart 15.

[0072] Therefore, even if the probe 14 is connected to the fourthconductive metal layer 34 and a part of the fourth conductive metallayer 34 adheres to the probe 14 (or to the plated part 15), the probe14 and the plated part 15 will not be degraded. Thus, since it is nolonger necessary to replace expensive the probes 14 frequently, thetesting cost can be reduced while increasing the reliability of the teststep.

[0073]FIG. 15 is a chart showing combinations of materials of the probe14 (or of the plated part 15, if any) and the third conductive metallayer 33, and possible materials of the fourth conductive metal layer34. The material of the probe 14 and the material of the thirdconductive metal layer 33 are used as parameters for specifying thematerial of the fourth conductive metal layer 34. The combination of thematerials of the fourth conductive metal layer 34 and the probe 14 isrelated to the material of the third conductive metal layer 33 whichprovided under the fourth conductive layer and which prevents thediffusion of the bump 35.

[0074] From FIG. 15, it can be seen that when the probe 14 (or theplated part 15) is made of palladium (Pd) and the third conductive metallayer 33 is made of nickel (Ni), a preferable material for the fourthconductive metal layer 34 is palladium (Pd) or gold (Au).

[0075] Similarly, when the probe 14 (or the plated part 15) is made oftungsten (W) and the third conductive metal layer 33 is made ofpalladium (Pd), a preferable material for the fourth conductive metallayer 34 is selected from a group consisting of gold (Au), silver (Ag),platinum (Pt) and rhodium (Rd).

[0076] Now, FIG. 13 is a diagram showing how the burn-in test, which isa type of a reliability test, is carried out on the semiconductor chip27. As shown in FIG. 13, the semiconductor chip 27 is mounted on atesting card 50 and then placed in a burn-in chamber 52. Then, a heatingprocess and a cooling process are alternately repeated. Thus, thesemiconductor chips which may cause a failure due to inherent weaknessor manufacturing variation will be removed. Therefore, the burn-in testmay be considered as a type of a screening test.

[0077] In the present embodiment, a burn-in test at 125° C. for 48 hoursis repeated twice. The test card 50 is provided with test terminals 51,such as stud bumps, and the test terminals 51 are respectively connectedto the barrier metals 30A of the semiconductor chip 27.

[0078] With the testing step of the present embodiment in which the testterminals 51 are brought in contact with the barrier metals 30A, whenthe above-described burn-in test is implemented, an oxide layer may beproduced at the surface of the fourth conductive metal layer 34.Accordingly, there is a risk that the joining property between the bumps35 and the barrier metals 30A may be degraded.

[0079] However, in the present embodiment, since the fourth conductivemetal layer 34 is made of a material having resistance to oxidization.Therefore, even if the heating process is carried out in the testingstep, the oxide layer will not be formed on the surface of the fourthconductive metal layer 34. Accordingly, in the protruded electrodeforming step (described later), the bump 35 can be securely joined onthe barrier metal 30A (the fourth conductive metal layer 34).

[0080] After the testing step described above, the protruded electrodeforming step is carried out. Solder balls of solder having a Pb/Sn ratioof 95%/5% are transferred onto the barrier metal 30A. Then, a reflowprocess is carried out under at 350° C. under nitrogen atmosphere.Thereby, the bump 35 having a height of about 100 μm are formed.Subsequently, processes such as cleaning the flux are implemented. Thus,the semiconductor device 20 shown in FIG. 14 is manufactured.

[0081] In the protruded electrode forming step, the reflow process (heattreatment) is implemented. However, since the fourth conductive metallayer 34 is made of a material which can be easily alloyed with the bump35, there is a risk that the fourth conductive metal layer 34 dissolvesand alloys with the bump 35.

[0082] However, in the present embodiment, the weight of the fourthconductive metal layer 34 is less than 2% (weight percentage) of theweight of the bump 35. Therefore, even if the fourth conductive metallayer 34 is entirely alloyed with the bump 35, the amount of the fourthconductive metal layer 34 in the bump 35 is considerably small. Thus,the degradation of the bump 35 can be prevented.

[0083] The fourth conductive metal layer 34 may be made of a materialwhich can be easily alloyed with the bump 35 so as to improve theelectrical connectivity and prevent the degradation of the probe 14 inthe testing step. However, as has been described above, the joiningforce between the bumps 35 and the barrier metals 30A can be maintaineddue to low amount of the fourth conductive layer 34. Thus, the bumps 35will not fall off when mounted on the semiconductor device 20, and themounting reliability of the semiconductor device 20 can be improved.

[0084] FIGS. 16 to 19 are diagrams showing various barrier metal formingsteps of a second embodiment of a method of manufacturing asemiconductor device of the present invention. In FIGS. 16 to 19, sameelements as those shown in FIGS. 4 to 14 are illustrated with samereference numerals.

[0085] The present embodiment is characterized in that the barrier metaldoes not include the third conductive metal layer 33 of the firstembodiment. In other words, the intermediate conductive layer mustinclude one of nickel (Ni) and palladium (Pd), since those material havehigh diffusion protection property. However, depending on materials ofother stacked layers, the intermediate conductive layer need not containcopper (Cu) which has a low diffusion protection property.

[0086] Therefore, in the present invention, the first conductive metallayer 31 is made of a material such as titanium (Ti). The secondconductive metal layer 32 is made of a material such as nickel (Ni) orpalladium (Pd). The fourth conductive metal layer 34 is made of amaterial such as gold (Au). In the present embodiment, the fourthconductive metal layer 34 is directly laminated on the second conductivemetal layer 32.

[0087] In order to manufacture the barrier metal of the presentembodiment, first of all, the first and second conductive metal coatings41, 42 are formed as shown in FIG. 16. Then, the resist 44 havingopenings 45 are formed on the second conductive metal coating 42. Then,as shown in FIG. 17, the fourth conductive metal layer 34 is directlyformed on the second conductive metal coating 42. Subsequently, as shownin FIG. 18, the resist 44 is removed. Thereafter, the unwanted parts ofthe first and second conductive metal coatings 41 and 42 are removed byetching, so as to provide the first and second conductive layers 31, 32,respectively. Thus, the barrier metal 30B having a triple-layeredstructure shown in FIG. 19 is formed.

[0088] It can be understood that the number of layers of the barriermetal can be altered by appropriately selecting the material of eachconductive metal layer. Therefore, the structure of the barrier metal isnot limited to the four-layered structure of the first embodiment or tothe triple-layered structure of the second embodiment, but can be alayered structure having five or more conductive metal layers. Even withthe layered structure having five or more conductive metal layers, if amaterial of the uppermost conductive metal layer is selected to have anappropriate property with the material of the bump (protrudedelectrode), the testing step can be implemented before the protrudedelectrode forming step.

[0089] In the above-described embodiment, first, the barrier metalforming step is implemented. Subsequently, the wafer 25 is diced so asto obtain individualized semiconductor chips 27. Therefore, in theabove-described embodiment, the testing step and the protruded electrodeforming step are implemented on the individualized semiconductor chips27.

[0090] However, it is inefficient to implement the testing step and theprotruded electrode forming step on each one of the individualizedsemiconductor chips 27. Thus, dicing can be implemented not immediatelyafter the barrier metal forming step. Instead, the testing step and theprotruded electrode forming step can implemented after the barrier metalforming step. The wafer 25 can be diced thereafter.

[0091] In this manner, the testing step and the protruded electrodeforming step can be simultaneously implemented on the plurality ofsemiconductor chips 27 formed on the wafer 25. Thereby, themanufacturing efficiency of the semiconductor devices can be improved.

[0092] Also, the protruded electrode forming step is implemented only onthose semiconductor devices which have been determined as goodsemiconductor devices during the testing step. Thus, the bumps 35 willnot be formed on bad semiconductor devices, so that a wasteful use ofbump material can be avoided.

[0093] Also, the above-described steps of selectively forming the bumps35 may be carried out in various transferring method where the bumps 35are transferred to the individualized semiconductor chip 27. Also, whenthe bumps 35 are formed on an undiced wafer, if bump forming method suchas metal jet method is employed, the bumps 35 may be only formed on goodsemiconductor chips based on the location data of bad semiconductorchips. With the metal jet method, the solder is expelled onto the wafer25 in a similar to ink jet method, so as to form the bumps.

[0094] Further, the present invention is not limited to theseembodiments, but variations and modifications may be made withoutdeparting from the scope of the present invention.

[0095] The present application is based on Japanese priority applicationNo. 11-118543 filed on Apr. 26, 1999, the entire contents of which arehereby incorporated by reference.

What is claimed is:
 1. A method of manufacturing a semiconductor deviceprovided with first electrodes formed on a semiconductor substrate andsecond protruded electrodes provided on said first electrodes,respectively, said method comprising the steps of: a) forming a barriermetal on each one of said plurality of first electrodes, said step a)further comprising the sub-steps of: laminating a lowermost conductivemetal layer on said first electrode, said lowermost conductive metallayer having a comparatively good joining property with said firstelectrode; laminating an intermediate conductive metal layer on saidlowermost conductive metal layer; and laminating an uppermost conductivemetal layer on said intermediate conductive metal layer, said uppermostconductive metal layer serving as a barrier layer for preventing saidsecond protruded electrode from being diffused in said first electrode;b) forming said second protruded electrodes on said barrier metals; andc) implementing one or more predetermined test on said semiconductorsubstrate by applying signals to said semiconductor substrate, whereinsaid step c) is carried out after said step a) and before said step b).2. The method as claimed in claim 1, wherein, in said step c), thesignals are supplied to the semiconductor substrate by contacting saidbarrier metals with probes.
 3. The method as claimed in claim 1, whereinsaid uppermost conductive metal layer is made of a material havingresistance to reaction and adhesion with the metal used for the probe.4. The method as claimed in claim 1, wherein said uppermost conductivemetal layer is made of a material which can be easily alloyed with thematerial of the protruded electrode and has resistance to oxidation. 5.The method as claimed in claim 1, wherein said step b) is implementedonly on those semiconductor chips which have been determined as goodsemiconductor chips during said step c).
 6. The method as claimed inclaim 1, said step b) further comprising the sub-steps of: forming afirst metal coating, which will become said lowermost conductive metallayer, on substantially the entire surface on said semiconductorsubstrate, said first metal coating having a layered structure of one ormore layer having a comparatively good joining property with said firstelectrodes; forming a second metal coating, which will become a part ofsaid intermediate conductive metal layer, on said first metal coating,said second metal coating having a layered structure of one or morelayer having a comparatively good joining property with said first metalcoating; forming third conductive metal layers, which will become a partof said intermediate conducive metal, by forming a resist provided withopenings at positions corresponding to said first electrodes and havingareas greater than the areas of the first electrodes, then forming thirdconductive metal layers in said openings such that the third conductivemetal layers cover the second conductive coating, said third metalconductive layers having layered structure of one or more layer having acomparatively good joining property with said second metal coating andto said second protruded electrodes; forming fourth conductive metallayers, which will become said upper most conductive metal layer, onsaid third conductive metal layer, said fourth conductive metal layershaving layered structure of one or more layer which easily alloys withthe material of the second protruded electrodes and has resistance tooxidation; forming first conductive metal layers and second conductivemetal layers by removing said first conductive metal coating and secondconductive metal coating while using the third conductive metal layerand fourth conductive metal layer as masks.
 7. The method as claimed inclaim 6, wherein a weight of the fourth conductive metal layer is lessthan 2% (weight percentage) of the weight of the protruded electrode. 8.The method as claimed in claim 6, wherein said first conductive metallayer is made of a metal chosen from a group consisting of titanium(Ti), chromium (Cr), molybdenum (Mo) and tungsten (W), or of an alloycontaining a metal chosen from a group consisting of titanium (Ti),chromium (Cr), molybdenum (Mo) and tungsten (W).
 9. The method asclaimed in claim 6, wherein said second conductive metal layer is madeof a metal chosen from a group consisting of copper (Cu), nickel (Ni)and palladium (Pd), or of an alloy containing a metal chosen from agroup consisting of copper (Cu), nickel (Ni) and palladium (Pd).
 10. Themethod as claimed in claim 6, wherein said third conductive metal layeris made of a metal chosen from a group consisting of copper (Cu), nickel(Ni) and palladium (Pd), or of an alloy containing a metal chosen from agroup consisting of copper (Cu), nickel (Ni) and palladium (Pd).
 11. Themethod as claimed in claim 6, wherein said fourth conductive metal layeris made of a metal chosen from a group consisting of gold (Au), platinum(Pt), palladium (Pd), silver (Ag) and rhodium (Rh) or of an alloycontaining a metal chosen from a group consisting of gold (Au), platinum(Pt), palladium (Pd), silver (Ag) and rhodium (Rh).
 12. The method asclaimed in claim 6, wherein said protruded electrode is made of a metalchosen from a group consisting of tin (Sn), lead (Pb), silver (Ag),indium (In) and bismuth (Bi) or of an alloy containing a metal chosenfrom a group consisting of tin (Sn), lead (Pb), silver (Ag), indium (In)and bismuth (Bi).
 13. A semiconductor device having a semiconductorchip, first electrodes formed on said semiconductor chip, barrier metalsformed on said first electrodes and having laminated structures, aplurality of second protruded electrodes, which serves as externalconnection terminals, formed on said barrier metals, said barrier metalcomprising: a lowermost conductive metal layer laminated on said firstelectrodes and made of one or more conductive metal coating having acomparatively good joining property with said first electrodes; anintermediate conductive metal layer laminated on said lowermostconductive metal layer and made of one or more conductive metal layerhaving a comparatively good joining property with said lowermostconductive metal layer, at least one of said conductive metal layersserving as a barrier layer for preventing said protruded electrodes fromdiffused into said conductive metal layers; and an uppermost conductivemetal layer laminated on said intermediate conductive metal layers andmade of one or more uppermost conductive metal layers made of a materialwhich easily alloys with the material of said plurality of the uppermostconductive metal layers.
 14. A method of manufacturing a semiconductordevice comprising the steps of: a) forming barrier metals on firstelectrodes provided on a chip of the semiconductor device; b)implementing, after said step a), a predetermined test on thesemiconductor device by applying a signal to the semiconductor devicevia at least one of the barrier metals; and c) forming, after said stepa), second protruded electrodes on the barrier metals.
 15. The method asclaimed in claim 14 wherein said step a) comprises a step of forming thebarrier metals each having a multilayer structure having uppermostconductive metal layer which is made of a material which can be alloyedwith a material of the second protruded electrodes and has a resistanceto reaction and adhesion with a material of probes used for said step b)and with a material of plated parts provided on the probes.